This invention relates to a semiconductor memory device which has a plurality of memory cells formed in a substrate.
Heretofore, a wide variety of semiconductor memory devices have been used in a lot of engineering fields with different purposes. As well known in the art, the semiconductor memory devices are generally classified into a read-only-memory (ROM) device and a random access memory (RAM) device which is readable and writable. It is also well known in the art that the latter RAM device is subdivided into a dynamic RAM (DRAM) device and a static RAM (SRAM) device. The DRAM needs to be refreshed to keep information while the SRAM can keep information as long as an electric voltage is impressed to the SRAM from a power source.
Among the above-enumerated semiconductor memory devices, the static RAM (SRAM) device is formed on a semiconductor substrate and has an array of memory cells arranged in rows and columns, a plurality of digit lines along the columns, and a plurality of word lines along the rows.
In this event, each of the memory cells is implemented by a flip-flop circuit and has generally a pair of drive transistors and a pair of information storage transistors, connected to the drive transistors to form the flip flop circuit, and a pair of selection transistors connected to the digit and the word lines.
Furthermore, the SRAM device further has a common line laid along each row and a substrate line for giving a substrate voltage to the substrate. A substrate voltage control circuit is connected to the common line and the substrate line to control a leak current which flows through the drive transistors of each memory cell towards the substrate. The substrate voltage control circuit is turned on or off in response to a chip enable signal common to all of the memory cells on the substrate.
With this structure, it is possible to reduce the leak current in the absence of the chip enable signal because the substrate voltage control circuit is kept in the off-state.
However, such a leak current can not be reduced when the substrate voltage generation circuit is turned on in response to the chip enable signal.
A wide variety of substrate voltage control circuits have been proposed, for example, in Japanese Unexamined Patent Publication Nos. Hei 4-281299 (281299/1992), and Hei 7-142688 (142688/1995). It is to be noted that such substrate voltage control circuits are never directed to an SRAM but to an EEPROM or a non-volatile memory device.
Alternatively, a substrate voltage control circuit disclosed in Hei 2-96998 (96998/1990) serves to prevent an inner logic circuit from being destroyed on occurrence of an excessive voltage in an RAM. Consideration is in this reference made at all neither about an SRAM or about a reduction of a leak current which flows through each drive transistor.